A pattern of a typical semiconductor device is designed with a designing unit realized by a computer. The designing unit performs arrangement of power supply wiring, cells, and signal lines based on the specification of the semiconductor device to generate pattern data for the semiconductor device.
The power supply wiring has a multilayer structure. For example, the power supply wiring includes first power supply lines formed in parallel on a given wiring layer, such as a sixth wiring layer, along a given direction, such as a direction X, and second power supply lines formed in parallel on a wiring layer, such as a fourth wiring layer, which is different from the aforementioned wiring layer along a direction perpendicular to the first power supply lines, such as a direction Y. The first and second power supply lines are formed like a lattice, mesh, or net when a semiconductor chip is seen from the side on which the wiring is formed, e.g., in a plane view. The power supply wiring includes vias formed at intersection points of the first and second power supply lines on the two distinct wiring layers for electrically coupling the first and second power supply lines, and vias for coupling the first and second power supply lines or the like to power wiring in an element.
An example of the above-described vias is a stack via. The stack via includes vias stacked in the direction in which wiring layers are formed. Two groups of wiring formed on the wiring layers located separate from each other, such as a first wiring layer and the fourth wiring layer, may be coupled through the stack via.
The signal lines of the semiconductor device are formed on lower layers of the above-described wiring layers and near a substrate. However, when a semiconductor device with a large number of signal lines is desired, use of only the wiring layers located lower than the fourth wiring layer on which the second power supply lines are formed may not be enough to form all of the desired signal lines. Therefore, in the designing unit, the signal lines may be formed also on the fourth wiring layer on which the power supply lines are formed and a fifth wiring layer located higher than the fourth wiring layer.
When the signal lines are formed on the fifth wiring layer, the vias are formed on channels for forming the signal lines and a shortage of the channels for forming the signal lines may be caused. When the shortage of the channels is caused, changes such as enlarging the chip area or increasing the wiring layers may be made. When such changes are made, it is preferable to start again from the arrangement operation of the power supply wiring, which is an earlier operation in the design operations.
In a conventional technique, the number of vias for coupling power supply lines is reduced to increase the number of wiring channels.
As described above, the reduction of the number of the vias may result in a lessening of a physical amount of the power supply material for supplying the power supply voltage, e.g., the cross-sectional areas of the power supply lines and/or vias. The physical amount of the power supply material is inversely proportional to an amount of the power supply voltage drop, called “IR drop”, from a pad to which external power is supplied to a cell located in a given position.
Thus, the conventional technique may not provide the cell in the given position with a desired power supply voltage.